1. Field of the Invention
The present invention relates to a hierarchical processing apparatus using a parallel operation for use in pattern recognition or the like and also to a method thereof.
2. Description of the Related Art
One known technique of image or speech recognition is to execute a recognition algorithm designed for a particular pattern on a computer. Another known technique is to perform image or speech recognition using a designated parallel image processor (such as a SIMD or MIMD).
A typical example of the image recognition algorithm is to calculate the similarity degree of a feature with respect to a model pattern to be detected. More specifically, model data indicating template models to be detected is prepared, and the similarity between an input image (or a feature vector thereof) and template models is determined by calculating, for example, the high-order correlation coefficient. It is known to use hierarchical parallel processing to determine the similarity.
In order to make it possible for a semiconductor integrated circuit to be used for a wide variety of image/speech recognition, Japanese Patent Laid-Open No. 6-274459 disclose a technique in which a semiconductor integrated circuit is formed of an electrically rewritable nonvolatile memory, a plurality of processors, and a programmable switch array for programmably connecting the plurality of processors, such that the connection among processors can be changed after completion of producing the semiconductor integrated circuit.
However, the former technique is poor in versatility, and the latter technique needs a large-scale circuit that needs high power consumption. Thus, there is a need for a versatile circuit capable of performing a wide variety of complicated calculations with a simple circuit configuration that needs low power consumption.
Japanese Patent Laid-Open Nos. 11-168185 and 2000-331113 disclose techniques of connecting analog processing elements in a reconfigurable fashion using a FPGA. In the technique disclosed in Japanese Patent Laid-Open No. 11-168185, a FPGA is disposed in one layer of a multilayer substrate, analog processing elements are disposed in another layer, and the FPGA and the analog processing elements are connected with each other via input/output terminals and an interface circuit. In the technique disclosed in Japanese Patent Laid-Open No. 2000-331113, first and second analog signals are converted into pulse width modulated (PWM) signals, and the resultant signals are input to a FPGA circuit, which performs a logical operation on the two PWM signals, thereby achieving reconfigurability.
Japanese Patent No. 2679730 discloses an architecture of realizing a hierarchical-structure neural network by using a single-layer hardware apparatus in a time-division multiplexed fashion such that the single-layer hardware apparatus virtually operates as a multilayer processing apparatus. More specifically, the neural network includes a set of single-layer neuron model units connected with each other. A time-division multiplexed analog signal is applied to each single-layer neuron model unit. The time-division multiplexed analog signal is multiplied by digital weight data supplied from the outside thereby time-sequentially obtaining products. The sum of the products is determined by time-sequentially adding (integrating) the products via a capacitor, and the resultant voltage is passed through a nonlinear output function and time-sequentially output. The outputs of the set of single-layer units are fed back to the inputs of the set of single-layer units via a feedback line. The operation of time-sequentially multiplexing the analog signals output from the respective units of the set of single-layer units and the feeding-back operation are performed under the control of a controller so that the set of single-layer units is used in the time-division multiplexed fashion thereby virtually realizing a hierarchical-structure neural network.
U.S. Pat. No. 5,959,871 discloses a FPAA (Field Programmable Analog Array) circuit including a multiplexer, demultiplexer, a controller, and programmable analog processing cells each including analog processing elements, wherein the analog processing cells are disposed in parallel via signal lines so that programmable analog processing can be performed.
In those techniques, the number of input/output terminals increases exponentially with the number of operation elements, and it becomes impossible to arbitrarily set a necessary interconnection structure. That is, no technique is known that perfectly meets the need for a small-scale low-power circuit capable of performing complicated parallel hierarchical processing.